A semiconductor device may include a cell region and a peripheral region. A plurality of memory cells for storing data may be formed in the cell region. The peripheral region may include a plurality of transistors. In particular, a voltage applied to the transistors of the peripheral region may be higher than a voltage applied to the memory cells of the cell region. Thus, the transistors of the peripheral region may have an isolation characteristic greater than a well of the cell region. A transistor having a deep Shallow Trench Isolation (STI) and a wide well structure is provided. However, the deep STI and wide well structure make it difficult to form a photoresist pattern during a pattering process.
Generally, a semiconductor device having a Silicon-On-Insulator (SOI) structure may be fabricated in a semiconductor substrate to improve the isolation characteristic of the device. The SOI substrate includes a semiconductor substrate, an insulating layer, and a silicon layer formed on the insulating layer. The transistors formed on the SOI substrate may have an improved isolation characteristic, a latch-up free property, and a low junction capacity of a source/drain junction. In particular, a complete depletion type SOI transistor enables low power consumption and a high-speed operation, may be driven at a low voltage.
However, the silicon layer formed on the insulating layer may have micro defects, such as grain boundaries and micro twins, thus it is not suitable to form the transistors of a micro pattern such as memory cell.